Hypotenusal square-rooting for c.r.t. display corrections and the like

ABSTRACT

Electronic corrections for pincushion-type distortions, promoting large and precise displays by short-length flat-faced large-area cathode ray tubes, are automatically produced at high speeds by miniature solid-state circuitry which introduces hypotenusal compensatory modifications into beam-deflection signals over wide deflection angles, the necessary square-rooting actions being those which take minimum electron-beam length into account and being developed by way of cooperating semiconductor devices whose characteristics and interactions force certain combined circuit currents to bear essentially square-root relationships to sums of squares of reference currents.

United States Patent 1191 Knitter June 5, 1973 HYPOTENUSALSQUARE-ROOTING FOR C.R.T. DISPLAY CORRECTIONS AND THE LIKE Inventor:James B. Knitter, Westwood, Mass.

Assignee: Intronics Mass.

Filed: Feb. 4, 1971 Appl. No.: 112,662

Incorporated, Newton,

U.S. c1...I .235/197, 235/193.5, 315/276 DC 511 1111.0. ..G06t 15/34 581Field of Search ..315/24, 27 TD, 27 01),

[5 6] References Cited UNITED STATES PATENTS 3,501,669 3/1970 Henderson..315 24 3,422,305 1/1969 Infante 3,517,252 6/1970 Williams... 3,308,3343/1967 Bryson ..3l5/276 0 3,422,306 1/1969 Gray ..315/276 D PrimaryExaminer-Benjamin R. Padgett Assistant Examiner-J. M. PotenzaAttorney-James E. Mrose and Mary C. Thomson [57] ABSTRACT Electroniccorrections for pincushion-type distortions, promoting large and precisedisplays by short-length flat-faced large-area cathode ray tubes, areautomatically produced at high speeds by miniature solid-state circuitrywhich introduces hypotenusal'compensatory modifications intobeam-deflection signals over wide deflection angles, the necessarysquare-rooting actions being those which take minimum electron-beamlength into account and being developed by way of cooperatingsemiconductor devices whose characteristics and interactions forcecertain combined circuit currents to bear essentially square-rootrelationships to sums of squares of reference currents.

22 Claims, 9 Drawing Figures PATENTEBJUH Elm 3.737.641

SHEET 1 BF 2 I INVENTOR:

i b JAMES B. KNITTER x ATTO RN EYS PATENTEU JU-H, 5|973 3, 737. 641

SHEET 2 0F 2 FIG.8 57

m 1X (II CLAMP +1 MMNW\ Q8 5 l k i" l/ 52 n O 2) 0 63 Wm o a. g L60 --0:3 5 --0 9 9 o 4 cr 1 i 5 Q2 Q1 1 H69 INV ENTOR= JAMES B. KNITTER by/MWM W ATTORNEYS HYPOTENUSAL SQUARE-ROOTING FOR C.R.T. DISPLAYCORRECTIONS AND THE LIKE BACKGROUND OF THE INVENTION The presentinvention relates to improvements in 5 electronic circuitry fordeveloping output signals related to the square root of the sum ofsquares of excitation signals, and in one particular aspect, to noveland improved high-precision miniature solid-state networks of relativelylow-cost and uncomplicated construction which are especially well suitedto wide-bandwidth corrections of distortions in cathode ray tubedisplays, notably correction of large-signal pincushion distortions inflat and semi-flat magnetically-deflected displays.

It is well known that optimum cathoderay tube designs for many purposesshould involve short tube lengths, large-area flat screens, and wideangles of elec-' tron-beam deflections. By way of example of theimportant uses which call for perfection of flat-faced precisiondisplays are: computer graphics; document reproduction; air trafficcontrol radar; and photo typesetting. However, because of practicalobstacles to precision displays by such tubes, their screens arecommonly fashioned with a speherical contour, the same being true ofassociated shadow masks in the case of color displays, and, where flatscreens are employed to offset errors such as those of parallax createdby curved screens, deflection angles and the resulting dimensions ofreproduced images must be kept very small to minimize inherentdistortions. A truly critical intrinsic distortion problem is thatassociated with so-called pincushion effects, resulting from the factthat, with in creasing horizontal and vertical deflection forcesexperienced by electrons in a C.R.T. beam, the drift paths to ultimateimpingements upon phosphor of a flat screen are increasingly long and,as a consequence of the longer drifts, the electrons will deflecthorizontally and vertically more than intended by the deflection forcesdeveloped back at the site of the deflection yoke. Efforts have beenmade to compensate by way of injecting electrical correction signals foreach further increment of horizontal and vertical deflection signals,but this technique necessarily entails discontinuities which restrictprecision, and, further, the related electronic-network implementationof this approach is of great complexity and expense. And, wheremathematical approximation has been relied upon as a prior basis fordeveloping continuous correction signals, the approximation has notproved to be a valid and successful solution to the difficultiesencountered with very wide angles of deflection, such as deflectionsabove 80. In addition to the aforesaid pincushion distortions, there areserious problems associated with maintenance of the exceedingly sharpbeam focus which is imperative in high-precision displays, because asthe beam is deflected over wide angles, the path lengths to impingementsupon a flat screen vary and do not correspond to that fixed minimumfocal length which produces a specific minute spot size at the center ofthe screen. Improved corrections for pincushion distortions, inaccordance with the present teachings, are continuously introduced byrelatively uncomplicated highly stable analog circuitry which uniquelytakes into account the minimum tube length from center of the deflectionto the screen, together with both instantaneous rectangular-coordinatedeflection signals, and which develops modified deflection signals basedupon a key recognition that the appropriate corrected signals arerespectively proportional to horizontal and vertical deflectionparameters each divided by the square root of the sums of the squares ofboth of these same parameters and the square of a minimum-tube-lengthparameter. Further, the recognitions and innovations extend to relatedfast wideband networks for implementing the precise electronicrepresentation of the square root by way of relatively non-criticalsolid-state circuit components.

SUMMARY The present invention is aimed at creating improved,high-precision, practical and reliable, analog electronic circuitrywhich produces output signals related to the square roots ofthe sums ofsquares of input signals and which operates efficiently both at highspeeds and with large variations in signals. A preferred embodiment ofsuch circuitry requires only solid-state semiconductor and resistanceelements, without involving inductance or capacitance; moreover, theresistances need not be of very close tolerance and the semiconductorsare relatively non-critical as to matching. Interactions which are ofkey importance are caused to occur by way of a four'terminalfour-transistor network comprising two pairs of series-connectedtransistors, each typically involving emitter-connected NPN and PNPtransistors, the bases of one series-connected pair being connectedacross the other series-connected pair, and each transistor of thelatter pair having its collector and base connected in common.Preferably, the base-emitter voltage drop characteristics of all thetransistors in the network are about the same, assuring a goodapproximate matching of reverse saturation current characteristics, andthe transistors have relatively low emitter resistance. Uniquely takingadvantage of intrinsic logarithmic non-linear characteristics of thetransistors, and, specifically that baseemitter voltages are closelyrelated to the natural log of the ratio of collector current to reversesaturation current, the network is forced to respond to two inputsignals, in current-related form, carried by way of two of itsterminals, and the remaining two terminals are then forced to yieldcurrents, through external paths, the sum of which is related to thesquare root of the sum of squares of the inputs as desired. For purposesof operation with input signals whose voltages represent the data ofinterest, voltageto-current converters may be used to make the neededtranslations, and, on the output side, an output voltage related to thesummed output currents, and, hence to the square root of the sum ofsquares of the input signals, is conveniently derived from thesecurrents by an operational amplifier functioning as a servo. Havingachieved a first square-rooting of a pair of input signals in theforegoing manner, the output may then be processed similarly with athird input signal, to derive a hypotenusal square-rooting in which theultimate output is instantaneously related to the square root of the sumof the squares of the three input signals. Where two of the signalsrepresent horizontal and vertical deflection signals to be applied to ashort flat-faced cathode ray tube, the third may be a constantrepresenting the minimum electron-beam length, and the output thencomprises a correction signal which serves to compensate forgeometry-induced distortions, such as so-called pincushion" distortionsand dynamic focus aberrations.

It is one of the objects of the present invention to provide novel andimproved electronic circuitry which achieves square-rooting accuratelyrelated to the sums of squares of signals, and which is of low-costmanufacture involving relatively non-critical components capable offunctioning at high speeds such as are requisite to uses in correctionof distortions in cathode ray tube displays.

Another object is to provide a unique solid-state wideband hypotenusalsquare-rooting network of relatively uncomplicated form lending itselfto miniaturized integrated-circuit embodiments and capable of reliablehigh precision operation.

A further object is to provide novel analog highspeed electronicsum-of-squares square-rooting circuitry wherein semiconductor devicessmoothly control the delivery of characterizing output signals, withoutbreakpoints.

Still further, it is an object of provide electrical networks in whichthe characteristics of a plurality of transistors distinctively forceoutput currents to assume a relation to input signals which is a preciseand continuous synthesis of the square root of the sum of squares ofinput signals.

In addition, it is an object to improve cathode ray tube displays byeliminating geometry-induced distortions inherent in short wide-angleflat tubes via precision corrections synthesized continuously and atappropriately high speeds from reference deflection signals and atube-length parameter, the corrections being forced to assume a criticalrelationship to the square root of sums of squares of the references byway of automatic control of current distributions in a currentresponsivenetwork.

BRIEF DESCRIPTION OF THE DRAWINGS Although the features of thisinvention which are considered to be novel are set forth in the appendedclaims, further details as to preferred practices and as to furtherobjects and advantages of the invention may be most readily comprehendedthrough reference to the following description taken in connection withthe accompanying drawings, wherein:

FIG. 11 is a partly schematic and partly cut-away pictorial illustrationof a flat-screen cathode-ray display tube, together with a graphicalrepresentation of deflection dimensions;

FIG. 2 presents a front view of the screen of the display tube of FIG.I, together with traces characterizing pincushion distortion;

FIG. 3 is a schematic diagram of a transistor network which promotes theproduction of output currents representative of the square root of thesum of squares of input currents;

FIG. 4 illustrates the network of FIG. 3 in association with auxiliaryvoltage-to-current converters which adapt the network for responses tovoltage signal inputs;

FIG. 5 represents the circuitry of a voltage-to-current converter whichmay typically be used in the circuitry of FIG. 8;

FIG. 6 provides a circuit diagram of a sum-of-squares square-rootingsystem involving electronic servo and clamping circuits assuringdevelopment of the desired square-root outputs;

FIG. 7 illustrates a modification of the system of FIG. 6 which allowsboth input signals to be of either polary;

FIG. 8 is a system diagram generally like that of FIG. 6 in whichcorrection is made of third-order effects, notably emitter resistances;and

FIG. 9 represents in block-and-schematic form a typical application ofthe correction circuitry of this invention, in a precision digital inputcathode ray tube display system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an aid to understanding ofsome of the difficulties which are resolved through practice of thisinvention, the protrayals in FIGS. 1 and 2 characterize certaindeflection problems encountered in cathode ray tubes. In FIG. 1, theneck of tube 10 is shown in association with an electron gun structure11 and horizontal and vertical electromagnetic deflection yoke coils 12and 13, and its substantially flat screen 14 carries a suitable phosphorcoating 15. The minimum distance or length of an electron beam from itscenter of yoke deflection to the center of the flat screen or face 14,is signified by the dimension L, and any horizontal deflection, x, forexample, necessarily entails the increased beam length equal to Vx LWhen a further deflection, y, occurs in the vertical direction, the beamlength increases correspondingly, to Vx y L Actual beam length at anyinstant may thus be calculated as the square root of the sums of squaresof a minimum beam-length parameter, L, and of horizontal and verticaldeflection factors x and y. Because electron speeds are unchanged bydeflection, variable beam lengths necessarily involve variable transisttimes for the electrons before their impingements upon the screenphosphor, and, minute as these times are, they are responsible forserious collateral non-linearities in the actual deflections whichoccur, because the lateral deflection velocities are created by and atthe yoke and are linearly related to the current in the yoke windings,and, thereafter, the actual total deflections are determined by theproduct of the lateral velocities and lengths of time the electronsremain in transit. It is for such reasons that the trace 16 of whatshould be substantially a square appears instead as an enlargeddistorted pincushion-like trace, in FIG. 2, whereas the intended x' andy deflections should have resulted in a trace like that characterized bydashed linework 17. Dynamic focus distortions, like so-calledpincushion" distortions, are affected by like considerations, and therelated difficulties are more pronounced as the tube lengths becomeshorter and the deflection angles are increased. Spherical contouring ofthe tube face, and associated non-uniform phosphor-dot patterns andshadow-mask apertures in the case of color display tubes tend to affectsuch difficulties somewhat, but at the expense of manufacturingcomplications. Moreover, precision CRT displays, involving minute spotsizes, are not accurately characterized for many purposes onspherically-contoured screens, and the problems which have been alludedto here have been resolved only in part through restriction ofdeflections to only a small central region in relatively long flat-facedtubes. Typical of the needs for exceedingly accurate broad-area displayson short flat-faced CRTs are: airtraffic control radar displays,computer graphics, document transmission and reproduction, andphototypesetting. Bandwidth requirements for electronicallyinducedcorrections of the distortions on a continuous basics are severe, andthere has been no known simple analog circuitry for achieving suchcorrections.

The aforesaid recognitions having to do with relation of distortionerrors to the square root of sums of squares of deflection factors areof special significance in implementation of the practice invention,inasmuch as it becomes possible to modify the deflection and/or dynamicfocus signals to take such errors into account in straightforwardfashion once that relation is expressed in electrical-signal form. Inthat connection, a key network for deriving the relation is presented inFIG..3,.wherein there are four semiconductor devices, 18-21, in apredetermined circuit relationship which responds to the currents in twoinput paths by yielding two output-path currents whose sum representsthe square root of the sum of squares of currents in the input paths.The illustrated devices 18 and are N-P-N transistors, and both of thetransistor pairs 18-19 and 20-21 have their emitters connected inseries. Collectors of the first transistor pair, 18-19, are intended tocarry the aforesaid two output-path currents, I and I respectively, andthe collectors of the second pair, 20-21, are connected in common withtheir respective bases and with the respective bases of the first pairof transistors. With one end of the seriesconnected pair 20-21 groundedand the other forced to conduct one of the input currents, I,,, relatedto a factor y, and with the series-connected emitters of the first pair,18-19, connected to respond to the other .input current, I,, related toa factor x, the sum of output-path currents l and I, can be shown to beaccurately representative of the square root of x and y That this occursis explained by considering the baseemitter voltage (V characteristicsand relationships in the four-transistor network. For transistors withvery large current gain connected as shown, the sum of base-emittervoltages for the series-connected pair 18-19 [V V must be the same asthe sum of base-emitter voltages for the paralled series-connected P20-21 wzm bel21)] 5 and, because it is recognized that the V,,, of eachof the transistors can be taken as KT/q In I substitution yields:

Where: K Boltzmanns constant,

T= Temperature (subscripts in parentheses designating the transistors),

I,,= common base current gain X emitter junction reverse saturationcurrent (subscripts in parentheses designating the transistors), and

q electron charge.

With temperatures of all junctions being substantially the same, as theyare in practical integrated-circuitry embodiments of the network wherethe junctions are close together, the equation simplifies to:

i/ ous) 1/ 000) u/ nuo) v/ mn and, because the logarithms translate asmultiplication:

Reverse current saturations (I 1 I and l are readily matched, as bydriving a reference current through transistors and selecting thosewhich have about the same voltage from base to emitter, V whereupon theequation reduces to:

It is also known that the collector currents for the first pair oftransistors, 18-19, are related as follows:

such that, with I, l /I and I, I,,'/I each being substituted in theequation I, 1,, I and I are defined I, 1, 1, 413/2 1 -I, w; 41, /2

and their sum is in the desired square-root relationship to the sum ofsquares of I, and I,,

In the foregoing, the relationship V KT/q in I U, for the transistors isof course an important factor, and related recognitions are based uponthe expression for collector current, as follows (Ebers-Moll equation):o n eo VbeIKT i co ycb [KT-l in which:

at,, common base current gain of the transistor $1 I emitter junctionreverse saturation current e 2718281828 q electron charge (1.602 X 10coulombs) V voltage from base to emitter K Boltzmanns constant, 1.38 Xl0- watt sec/"K T temperture (K) a, inverted common base current gain z1 I collector junction reverse saturation current V voltage, collectorto base If V is zero, the second term drops out, leaving:

I, at, 1 (e' "be'" l) Letting a be represented by I, then:

For the assumed condition where q V [KT l I, I, e" "be and V then equalsKT/g 1n 1,,, as indicated earlier herein.

Where pincushion distortions are to be corrected, for example, thecurrent 1 in the horizontal deflection coil should be corrected inrelation to the horizontal deflection signal, x, such that it will be:

1 k [x/ l Vy L 2 and the current I in the vertical deflection coilshould be corrected in relation to the horizontal deflection signal,such that it will be:

where k is an appropriate constant and L the aforesaid minimum beamlength. A network such as that of FIG. 3 accomplishes square-rooting ofthe sum of two squared terms, at high speed, and the above-noted desiredcorrections involving three terms may be developed by square-rootingtwice, using one such network for two of the terms and then a secondsimilar network for the third term and the square root of the sum ofsquares for the first two terms.

FIG. 4 illustrates the same network as that of FIG. 3, together withassociated voltage-to-current converters (V-l) 22 and 23 whichrespectively determine the currents I, and I, in response to the inputvoltages V, and V,,. The latter voltages applied at terminals 24 and 25of the network, may typically be the horizontal and vertical deflectionsignals intended for a CRT display tube, and from which pincushioncorrection signals are to be derived by way of electronicsquare-rooting. Details of one suitable embodiment for these convertersappear in FIG. 5, which is an example of the circuitry for converter 22.There, a differential pair of transistors 26 and 27 is supplied by wayof a constant-current source circuit 28, and the collector paths of thetransistors are coupled to a current-recirculation circuit 29, in aknown manner. Differences between the input voltage, V,,, applied at thebase of transistor 26 and a reference voltage level maintained at thebase of transistor 27, shown grounded, yield related differences incollector currents, and, in turn, establish the desired output current,1,. A similar converter serves to provide a suitable current input, I,,,in response to the deflection-voltage signal V,,. In other applicationsof the square-rooting network, such converters may not be necessary ifcurrent inputs are available directly, and/or the conversions to currentmay be made responsive to factors other than voltage, such as force orlight intensity.

In FIG. 6, the network and converter combination of FIG. 4 is furtherassociated with two auxiliary circuits, one of which, 30, keeps thecollector-to-base voltage, V of transistor 19 equal to zero, a conditionwhich was referred to hereinabove in the analysis of network function.The second auxiliary circuit, 31, which is in the nature of a servo,keeps the collector-to-base voltage, V of transistor 18 equal to zero,and thereby satisfies the same required condition for the lattertransistor also. The clamping circuit 30 fulfills not only the functionof holding the collector of transistor 19 at a fixed voltage but, inaddition, provides a needed current path for the collector-path currentI, For these purposes, a transistor 32 with its emitter-collector pathin series with the collector of transistor 19 has its base in serieswith a constant-current source 33, which may be like circuit 28 of FIG.5, the source 33 being parallelled with a series of three diodes 34which serve a temperature-compensation or tracking function in relationto the opposed transistor diode" drops. Further, the currentrecirculator 35, which may be like circuit 29 of FIG. 5, assures thatcurrent I, is of the correct direction in a branch connection 36 with asupply lead 37 from which current I is also drawn through a branch 38 tothe collector of transistor 18. Servo circuit 31, involving anoperational amplifier 39 and associated feedback resistance R,,,,develops an output voltage at terminal 41 which is in the intendedaccurate relationship to the sum of I, and 1,, and, therefore, to thesquare root of the sum of the squares of the system input voltages V,and V,,, the latter voltages in turn characterizing the factors .1: andy, respectively. The functions of auxiliary clamping circuitry 30 may beestablished in ways other than that specifically illustrated. By way ofexample, a reference voltage source combined with a circuit providing apath for current I, will have the intended effects; this may take theform of an operational amplifier supplying voltage to the base oftransistor 32 in FIG. 6, with the two-inputs to the operationalamplifier being taken from connections with the base and collector oftransistor 19.

The input signal V, in FIG. 6 may be either positive or negative,although the circuitry operates properly only when the current I, is inthe illustrated direction. However, V, may be allowed to be eitherpositive or negative when the circuitry is modified as shown in FIG. 7.There, the network will be seen to be generally as depicted anddescribed in relation to FIG. 6, except that a cascode arrangement isemployed, with the input from the V,, converter 23 being to theseries-connected emitters of a pair of transistors 42 and 43, much as inthe case of the input from the V, converter 22. The

base of transistor 42 has its voltage level set by diodes 44, and afurther diode, 45, across the bases of transistors 42 and 43, serves toreduce the voltage needed to turn these transistors on, therebyincreasing speed of operation; all of these diodes are in series with aconstant-current source 46 and the series-connected diodes are in turnconnected to clamp 30. A current recirculator 47, which may be likecircuits 29 and 35, couples the collectors of transistors 42 and 43, andtheir collector circuits are joined with the common base emitter oftransistor 21 in the same manner as was converter 23 in FIG. 6. Bothinput signals V, and V,, may then have either positive or negativeexcursions, with the output at terminal 41 characterizing the squareroot of the sums of their squares.

Operation of each of the four transistors 18-21 in the square-rootingnetwork is found to be affected somewhat by certain parasiticresistances the effects of which are represented by resistances R R Rand R in series with the emitters of transistors of number correspondingto these subscripts, in FIG. 8. It is understood that the effects ofthese resistances are developed partially by resistances in the emittersand partially in the bases of the transistors. One of their unwantedeffects is that, because current I, flows in and develops voltagesacross R and R the voltages appearing at the bases of transistors 18 and19 are correspondingly spread apart and may be so spread as to detractfrom the desired logarthmic relationship set forth hereinabove. However,the preferred optimum conditions are restored by changing theconnections of transistors 20 and 21 from those described earlierherein, and by inserting a compensating resistance R between them.Specifically, this is shown in FIG. 8 as involving use of a P-N-Ptransistor for transistor 20, its emitter being coupled with the base oftransistor 18 and its base being connected with its collector via thecompensating resistance R and as involving use of an N-P-N transistorfor transistor 21, its emitter being coupled with the base of transistor19 and its base being connected with its collector via the samecompensating resistance R,,,, albeit in the opposite direction. Thisresults in the collectors of the two transistors 20 and 21 beingconnected in series through resistance R and, more significantly forcompensation purposes, the voltage drop across R due to flow of current1,, through it substracts from the voltage drops across R and RReistance R is selected to be about the same as the sum of R and R suchthat these voltage drops are in offsetting relation, to effect one ofthe desired compensations. Therefore, insofar as the unwanted influencesof the parasitic resistances and current 1,, are concerned, theresistance and voltage-drop effects are eliminated, leaving unimpairedthe intended logarithmic influences of the junctions of transistors 20and 21 in he network.

There are also kindred problems arising out of the resistances R and Rand these are treated separately because currents I, and I, are notnecessarily equal, nor

equal to current I,,. In relation to these effects, the desiredcompensation voltage is equal to [,R 1 R and, because R and R are madeequal by approriate selection of transistors 18 and 19, the compensationvoltage equals R (1, 1,). Conveniently, the output voltage at terminal41 is proportional to I I and may simply be divided by way of a pair ofresistances R and R: to yield a compensating voltage, across R equal tothe aforesaid voltage R (I I The prescribed compensation is realizedwhen R R /R ,,+R,, is made equal to resistance R which is the same as RIn the arrangement shown, the compensation voltage appears between baseof transistor 18 and the net work ground, although this is not alimiting feature.

The diagram appearing in FIG. 9 typifies an application of thehypotenusal square-rooting circuitry for correction of the inputs in aprecision digital input display system. There, the varioussquare-rooting networks which are needed are incorporated into compactmodule 51 in which the semi-conductor junctions are advantageouslyproximate and are physically caused to be preserved at about the sametemperature, there being no tendency for any of the semiconductors todevelop localized hot spots in circuitry of the type which have beendescribed. SUch a module responds to horizontal input voltage appliedvia line 52 and to vertical input voltage applied via line 53, andresponds by delivering the needed corrected horizontal and verticaldeflection signals to horizontal and vertical deflection amplifiers 54and 55, respectively, for precision excitation of the horizontal andvertical deflection yoke coils 56 and 57, respectively, to eliminatepincushion-type errors from a precision falt-faced display CRT (notshown). The same type of square-rooting is exploited to developcorrected dynamic-focus signals, which are applied to dynamic focusamplified 58 exciting the dynamic focus coil 59. in this illustrativesystem application, a digital input at terminal 60 controls a charactergenerator 61 wich delivers horizontal and vertical output signals tolines 62 and 63, respectively. Digital inputs are also applied to thehorizontal and vertical digital-to-analog circuits 64 and 65,respectively, which are associated with sample hold circuits 66 and 67,respectively. Summing amplifiers 68 and 69 appear in the respectivehorizontal and vertical deflection-signal channels, providingappropriate excitations for input lines 52 and 53 to the correctionmodule.

It should be understood that the specific embodiemnts and practicesdescribed herein have been presented by way of disclosure rather thanlimitation, and that those skilled in the art will appreciate thatvarious modifications, combinations and substitutions may be effectedwithout departure from the spirit and scope of this invention in itsbroader aspects and as set forth in the appended claims.

What I claim as new and desire to secure by Letters Patent of the UnitedStates is:

l. Circuitry for characterizing the square root of sums of squares ofinputs, comprising a plurality of semi-conductor devices, meansinterconnecting said devices in a network relationship, said networkrelationship involving current paths through different ones of saiddevices, means forcing current flow in one of the paths to involvecurrent representing a first input, means forcing current flow inanother of the paths to involve current representing a second input,said interconnecting means maintaining the product of currents in saiddevices in said one of the paths equal to the square of currentrepresenting said second input in said other of said paths andmaintaining the difference in currents in said devices in said one ofthe paths equal to the current representing said first input in said oneof the paths, whereby the currents in said devices in said one of thepaths are related to the square root of the sums of squares of saidfirst and second inputs.

2. Circuitry for characterizing the square root of sums of squares ofinputs, comprising a first current path including semiconductor devices,means forcing the current flow through one of said semiconductor devicesto involve the sum of current through another of said devices and ofcurrent representing a first input, a second current path, means forcingcurrent flow through said second path to involve current representing asecond input, and means coupling said paths together into a networkrelationship wherein the product of currents through said semiconductordevices is substantially equal to the square of said currentrepresenting said second input, whereby the currents through saiddevices are related to the square root of the sums of squares of saidfirst and second inputs.

3. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 2 wherein said first current path includesa pair of transistors connected in series, and wherein said secondcurrent path includes semiconductor devices, said coupling meansincluding means applying voltages associated with said semiconductordevices in said second current path to control electrodes of saidtransistors.

4. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 3 wherein said transistors comprise NPN andPNP transistors having their emitters interconnected, wherein saidcurrent representing said first input is coupled with said first path atthe junction of said emitters, and wherein said means applying voltagesapplies said voltages to the bases of said transistors.

5. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 4 wherein said semiconductor devices insaid second path comprise a pair of series-connected transistors havingtheir bases connected with their collectors, said voltages being thevoltages at ends of the series connection of said series-connectedtransistors, and wherein said means forcing current through said secondpath forces current representing said second input through saidseries-connected transistors.

6. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 5 wherein said inputs are in the form ofvoltages, and wherein each of said means forcing current includes avoltageto-current converter responsive to different ones of saidvoltages.

7. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 5 wherein said pair of series-connectedtransistors comprises NPN and PNP transistors having their emittersinterconnected and each having its common emitter-and collectorconnected with a different one of the bases of the transistors in saidfirst current path.

8. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 5 wherein said pair of series-connectedtransistors comprises NPN and PNP transistors each having its emitterconnected with a different one of the bases of the transistors in saidfirst current path and each having its base connected with its collectorin a different direction through a compensating resistor, saidcompensating resistor having a resistance substantially equal to the sumof effective emitter resistances of said series-connected.

transistors.

9. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim wherein the reverse current saturationcharacteristics of all of said transistors are substantially the same,whereby the base-to-emitter voltages of all of said transistors aresubstantially the same for the same current therethrough.

10. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 4 further comprising means clamping thevoltage of the collector of one of said transistors to a voltagesubstantially the same as that at its base.

11. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 4 further comprising a current recirculatorrecirculating the collector-circuit current flowing through one of saidtransistors, and means producing output voltages related to the sum ofthe collector-circuit currents through said transistors, whereby saidoutput voltages are related to the square root of the sums of squares ofsaid first and second inputs.

12. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 11 wherein said means producing outputvoltages comprises an operational amplifier delivering saidcollector-circuit currents to said reflector and to the collectorcircuit of the other of said transistors and producing said outputvoltages related to the sum of said collector-circuit currents.

l3. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 8, further comprising means producingoutput voltage related to the sum of collector-circuit currents throughsaid transistor in said first path, voltage-dividing means dividing outof said output voltages compensation voltages substantially equal to thesum of voltage drops across effective emitter resistances of saidtransistors in said first path, and means coupling said compensationvoltages in series opposition to said voltage drops.

14. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 13 wherein the effective emitterresistances of said transistors in said first path are substantially thesame, and wherein said compensation voltages are substantially equal tothe product of said effective emitter resistance and the sum of saidcollector-circuit currents through said transistors in said first path.

15. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 6 wherein said means forcing currentthrough said second path includes a series-connected pair of auxiliarytransistors having their emitters interconnected and their collectors inseries with said second path and a voltage source, current recirculatormeans interconnecting the collector circuits of said auxiliarytransistors, means applying predetermined voltages to the bases of saidauxiliary transistors, and means applying current from thevoltage-to-current converter which is responsive to voltagesrepresenting said second input to the interconnected emitters of saidauxiliary transistors, whereby said circuitry responds to voltages ofeither polarity representing said second input.

16. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube, comprising a firstnetwork including first and second current flow paths, a pair oftransistors connected in series in said first path, means forcing thecurrent flow through one of said transistors to involve the sum ofcurrent through the other of said transistors and a first currentrepresenting to at least one of three magnitude factors comprisinghorizontal deflection signal, vertical deflection signal, and a minimumelectron beam length for the cathode ray tube, semiconductor devices insaid second path, means forcing current flow through said second path toinvolve a second current representing at least one other of said threefactors, and means coupling said paths together in a networkrelationship wherein the product of currents through said transistors issubstantially equal to the square of said second current, said couplingmeans including means applying voltages associated with saidsemiconductor devices in said second path to control electrodes of saidtransistors, whereby the sum of currents through said transistors isrelated to the square root of the sums of squares of factors among saidthree factors.

17. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube as set forth inclaim 16 wherein said transistors in each pair have their emittersinterconnected, wherein said first current representing at least one ofsaid factors is coupled with said first path at the junction of saidemitters, wherein said semiconductor devices in said secon path comprisea pair of seriesconnected transistors having their bases connected withtheir collectors, and wherein said means applying voltages appliesvoltages at the ends of said seriesconnected transistors to the bases ofthe transistors in said first path.

18. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube as set forth inclaim 17 wherein the reverse current saturation characteristics of allof said transistors are substantially the same, and further comprisingmeans clamping the voltage of the collector of said one of saidtransistors in said first path to a voltage substantially the same asthat at its base, a current recirculator recirculating thecollector-circuit current flowing through said one of said transistors,and means characterizing the sum of the collector-circuit currentsthrough said transistors in said first path.

19. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube as set forth inclaim 18 wherein said transistors in each of said paths comprise a NPNand PNP transistor, and operational amplifier means producing outputvoltages related to said sum of the collector-circuit currents.

20. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube as set forth inclaim 17 wherein one of said first and second currents is directlyrelated to two of said three factors.

22. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube as set forth inclaim 21 comprising a second network the same as said first network anddeveloping the said other of said currents.

1. Circuitry for characterizing the square root of sums of squares ofinputs, comprising a plurality of semi-conductor devices, meansinterconnecting said devices in a network relationship, said networkrelationship involving current paths through different ones of saiddevices, means forcing current flow in one of the paths to involvecurrent representing a first input, means forcing current flow inanother of the paths to involve current representing a second input,said interconnecting means maintaining the product of currents in saiddevices in said one of the paths equal to the square of currentrepresenting said second input in said other of said paths andmaintaining the difference in currents in said devices in said one ofthe paths equal to the current representing said first input in said oneof the paths, whereby the currents in said devices in said one of thepaths are related to the square root of the sums of squares of saidfirst and second inputs.
 2. Circuitry for characterizing the square rootof sums of squares of inputs, comprising a first current path includingsemiconductor devices, means forcing the current flow through one ofsaid semiconductor devices to involve the sum of current through anotherof said devices and of current representing a first input, a secondcurrent path, means forcing current flow through said second path toinvolve current representing a second input, and means coupling saidpaths together into a network relationship wherein the product ofcurrents through said semiconductor devices is substantially equal tothe square of said current representing said second input, whereby thecurrents through said devices are related to the square root of the sumsof squares of said first and second inputs.
 3. Circuitry forcharacterizing the square root of sums of squares of inputs as set forthin claim 2 wherein said first current path includes a pair oftransistors connected in series, and wherein said second current pathincludes semiconductor devices, said coupling means including meansapplying voltages associated with said semiconductor devices in saidsecond current path tO control electrodes of said transistors. 4.Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 3 wherein said transistors comprise NPN andPNP transistors having their emitters interconnected, wherein saidcurrent representing said first input is coupled with said first path atthe junction of said emitters, and wherein said means applying voltagesapplies said voltages to the bases of said transistors.
 5. Circuitry forcharacterizing the square root of sums of squares of inputs as set forthin claim 4 wherein said semiconductor devices in said second pathcomprise a pair of series-connected transistors having their basesconnected with their collectors, said voltages being the voltages atends of the series connection of said series-connected transistors, andwherein said means forcing current through said second path forcescurrent representing said second input through said series-connectedtransistors.
 6. Circuitry for characterizing the square root of sums ofsquares of inputs as set forth in claim 5 wherein said inputs are in theform of voltages, and wherein each of said means forcing currentincludes a voltage-to-current converter responsive to different ones ofsaid voltages.
 7. Circuitry for characterizing the square root of sumsof squares of inputs as set forth in claim 5 wherein said pair ofseries-connected transistors comprises NPN and PNP transistors havingtheir emitters interconnected and each having its common emitter-andcollector connected with a different one of the bases of the transistorsin said first current path.
 8. Circuitry for characterizing the squareroot of sums of squares of inputs as set forth in claim 5 wherein saidpair of series-connected transistors comprises NPN and PNP transistorseach having its emitter connected with a different one of the bases ofthe transistors in said first current path and each having its baseconnected with its collector in a different direction through acompensating resistor, said compensating resistor having a resistancesubstantially equal to the sum of effective emitter resistances of saidseries-connected transistors.
 9. Circuitry for characterizing the squareroot of sums of squares of inputs as set forth in claim 5 wherein thereverse current saturation characteristics of all of said transistorsare substantially the same, whereby the base-to-emitter voltages of allof said transistors are substantially the same for the same currenttherethrough.
 10. Circuitry for characterizing the square root of sumsof squares of inputs as set forth in claim 4 further comprising meansclamping the voltage of the collector of one of said transistors to avoltage substantially the same as that at its base.
 11. Circuitry forcharacterizing the square root of sums of squares of inputs as set forthin claim 4 further comprising a current recirculator recirculating thecollector-circuit current flowing through one of said transistors, andmeans producing output voltages related to the sum of thecollector-circuit currents through said transistors, whereby said outputvoltages are related to the square root of the sums of squares of saidfirst and second inputs.
 12. Circuitry for characterizing the squareroot of sums of squares of inputs as set forth in claim 11 wherein saidmeans producing output voltages comprises an operational amplifierdelivering said collector-circuit currents to said reflector and to thecollector circuit of the other of said transistors and producing saidoutput voltages related to the sum of said collector-circuit currents.13. Circuitry for characterizing the square root of sums of squares ofinputs as set forth in claim 8, further comprising means producingoutput voltage related to the sum of collector-circuit currents throughsaid transistor in said first path, voltage-dividing means dividing outof said output voltages compensation voltages substantially equal to thesum of voltage drops across effective Emitter resistances of saidtransistors in said first path, and means coupling said compensationvoltages in series opposition to said voltage drops.
 14. Circuitry forcharacterizing the square root of sums of squares of inputs as set forthin claim 13 wherein the effective emitter resistances of saidtransistors in said first path are substantially the same, and whereinsaid compensation voltages are substantially equal to the product ofsaid effective emitter resistance and the sum of said collector-circuitcurrents through said transistors in said first path.
 15. Circuitry forcharacterizing the square root of sums of squares of inputs as set forthin claim 6 wherein said means forcing current through said second pathincludes a series-connected pair of auxiliary transistors having theiremitters interconnected and their collectors in series with said secondpath and a voltage source, current recirculator means interconnectingthe collector circuits of said auxiliary transistors, means applyingpredetermined voltages to the bases of said auxiliary transistors, andmeans applying current from the voltage-to-current converter which isresponsive to voltages representing said second input to theinterconnected emitters of said auxiliary transistors, whereby saidcircuitry responds to voltages of either polarity representing saidsecond input.
 16. Circuitry for developing electrical output signals forthe correction of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube, comprising a firstnetwork including first and second current flow paths, a pair oftransistors connected in series in said first path, means forcing thecurrent flow through one of said transistors to involve the sum ofcurrent through the other of said transistors and a first currentrepresenting to at least one of three magnitude factors comprisinghorizontal deflection signal, vertical deflection signal, and a minimumelectron beam length for the cathode ray tube, semiconductor devices insaid second path, means forcing current flow through said second path toinvolve a second current representing at least one other of said threefactors, and means coupling said paths together in a networkrelationship wherein the product of currents through said transistors issubstantially equal to the square of said second current, said couplingmeans including means applying voltages associated with saidsemiconductor devices in said second path to control electrodes of saidtransistors, whereby the sum of currents through said transistors isrelated to the square root of the sums of squares of factors among saidthree factors.
 17. Circuitry for developing electrical output signalsfor the correction of display distortions resulting from variablelengths of deflected electron beam paths in a cathode ray tube as setforth in claim 16 wherein said transistors in each pair have theiremitters interconnected, wherein said first current representing atleast one of said factors is coupled with said first path at thejunction of said emitters, wherein said semiconductor devices in saidsecon path comprise a pair of series-connected transistors having theirbases connected with their collectors, and wherein said means applyingvoltages applies voltages at the ends of said series-connectedtransistors to the bases of the transistors in said first path. 18.Circuitry for developing electrical output signals for the correction ofdisplay distortions resulting from variable lengths of deflectedelectron beam paths in a cathode ray tube as set forth in claim 17wherein the reverse current saturation characteristics of all of saidtransistors are substantially the same, and further comprising meansclamping the voltage of the collector of said one of said transistors insaid first path to a voltage substantially the same as that at its base,a current recirculator recirculating the collector-circuit currentflowing through said one of said transistors, and means characterizingthe sum of the collector-circuit currents through said transistors insaid first path.
 19. Circuitry for developing electrical output signalsfor the correction of display distortions resulting from variablelengths of deflected electron beam paths in a cathode ray tube as setforth in claim 18 wherein said transistors in each of said pathscomprise a NPN and PNP transistor, and operational amplifier meansproducing output voltages related to said sum of the collector-circuitcurrents.
 20. Circuitry for developing electrical output signals for thecorrection of display distortions resulting from variable lengths ofdeflected electron beam paths in a cathode ray tube as set forth inclaim 17 wherein one of said first and second currents is directlyrelated to one of said three factors and the other of said currents isdirectly related to one other of said three factors.
 21. Circuitry fordeveloping electrical output signals for the correction of displaydistortions resulting from variable lengths of deflected electron beampaths in a cathode ray tube as set forth in claim 17 wherein one of saidfirst and second currents directly represents one of said three factorsand the other of said currents represents square root of the sums ofsquares of the other two of said three factors.
 22. Circuitry fordeveloping electrical output signals for the correction of displaydistortions resulting from variable lengths of deflected electron beampaths in a cathode ray tube as set forth in claim 21 comprising a secondnetwork the same as said first network and developing the said other ofsaid currents.